【第九期】 华进论坛:Microstructure Analysis of Copper Electrodeposits by Using Electron Backscattered Diffraction

2014-07-25

时间:2014年7月23日(星期三)9:30-11:30

地点:NCAP F6培训室

主讲人:Hyo-Jong Lee教授

讲座性质:公开

参与对象:公司全体研发人员

主办单位:华进半导体封装先导技术研发中心有限公司

支持单位:先进封装技术联合体

 

【讲座概要】

Cu has been widely applied to PCB (printedcircuit board) interconnection material, BEOL(back end of line) interconnect ina semiconductor and Cu line in large-area, high-resolution flat panel displaysby replacing prior Al wiring. However, Cu is a considerable anisotropicmaterial unlike Al, and then causes new reliability issues. Here, we will showyou the crystallographic texture analysis in copper electrodeposits and itsrelated phenomena; anisotropic grain growths and stress-induced voiding. Firstof all, the preferred crystallographic orientation of as-deposited filmsdepends strongly on the seed layer orientation deposited on a substrate, and itis also influenced by the plating conditions; current density, ionconcentration, temperature etc. Cu seed layer was deposited on a Si substratewith a diffusion layer of TaN or TiN by using a sputtering method, and hadgenerally the preferred (111) orientation for its plane normal direction. Theelectrolytically-deposited Cu film on the seed layer had the similar (111)preferred orientation. The electrodeposited layer was also been influenced bythe plating conditions. According to Lee, (111) fiber texture is evolved at thecondition of high current density, low concentration of Cu2+ and relatively lowtemperature of solution, and vice versa (100) texture is well developed. [DongNyung Lee, Texture and Related Phenomena, The Korean Institute of Metals andMaterials 2006, Hanrimwon Publishing Company, p.248-250] As the as-depositedfilm having many crystalline defects is very high energy state, therecrystallization occurs under an optimal condition and its recrystallizationtexture is correlated with stress field and surface energy as well as theinitial texture. In case of the line pattern fabricated by damascene process,the recrystallization texture depends on the pattern width. The plane normaldirection in the narrow pattern was maintained as <111> orientation andthe line direction appeared as <110> orientation. By stress calculation,the maximum strain field existed on the plane normal to the line direction, andthe <100> direction having the lowest elastic modulus has to be alignedon the plane in order to minimize the elastic strain energy. For example, [011̅ ]  direction was well matched with theline direction because [011 ̅ ] direction is normal to both [111] and [100].

In situ EBSD (electron backscattereddiffraction) measurement of grain growth during self-annealing was performed onthe copper electrodeposits with a thickness of 1 ㎛. As thefilm thickness is very thin, it can be assumed that regarding the film as 2Dstructure, the grain growth appearance on the surface is very similar with thatof the inner region and it is possible to estimate overall grain growth bymeasuring the grain growth on the surface. The in situ inspection resultsshowed that newly created twin appeared at a growing front and grew into thenon-grown(as-deposited) region. In addition, most of twin boundaries were {111}∑3 CSL(coincident site lattice) boundary and the twins grew along the<111> direction. These results suggested an important thing that thegrain growth direction is normal, not parallel, to twin boundary and it isopposite to the conventional theory. [P. J. Goodhew, Met. Sci. J. 13, pp.108-112 (1979), H.-J. Lee et al., Appl. Phys. Lett. 89, 161924:1-3(2006)]

We researched the interconnection failurethat a voiding occurred at the contact area with a via, and the void was foundin a particular crystallographic region by using FIB(focused ion beam)-EBSDcoupled technique.[H.-J. Lee et al., Appl. Phys. Lett. 92, 141917:1-3(2008)]After HTS(hot temperature storage) test, we investigated the voiding surface,and it was found out that most of voids happened near a triple junction andthrough cross-sectional EBSD analysis by FIB, the voiding grain had arelatively higher equi-biaxial elastic modulus. Namely, Si substrate has higherCTE(coefficient thermal expansion) than Cu, and copper is compressive stressstate at a high temperature of 200℃. Vacancies areaccumulated at a relatively higher stress region and the void can be formed.Such results show that even crystallographic difference can cause voids in theCu films.

Finally, I will show you my recent researchprojects, for Cu pillar bump, Cu foil, and PCB pattern which are co-worked withSamsung Electronics, Samsung Electro-Mechanics and LS Mtron.